1. Field of the Invention
The invention relates to a circuit device and a manufacturing method of the same, used for transmitting and receiving wireless telecommunications equipments such as a wireless LAN, ETC, and cellular phones, etc., and especially to a semiconductor integrated circuit device and a manufacturing method of the same which contains a high frequency thin film coil or the like.
2. Description of the Prior Art
As for the wireless equipments such as the wireless LAN, ETC, and cellular phones, etc. downsizing comes to be demanded by recent market trend more and more. It has been taken widely in recent years that an industrial method uses metallic bumps for electrical connections provided on a Si-IC substrate (bare IC chip) of the equipments and connects the Si-IC substrate on a surface of other substrate through the bumps by flip chip bonding, etc.
By the way, it has been made an universal method of using Al (aluminum) wiring patterns on the Si-IC substrate from a viewpoint of productivity etc., and it has been widespread that the method of forming the metallic bump to connect to an electrode paid which is exposed from a passivation film insulating the surface of the Si-IC substrate.
In case of the circuit device like the above-mentioned is made, voids may be formed because of diffusion phenomenon if the metallic bump of Au (gold) etc. directly formed on the Al film used as the wiring patterns might invite decrease in joint strength. As a result, characteristic of the circuit device might be influenced by the decrease in joint strength and the problem is caused in reliability.
To evade such diffusion phenomenon, at least an under bump metal (UBM) is formed with designated thickness on the surface of the electrode pad pattern of the Al film by an under bump metal processing (UBM processing). Concretely, a Ni (nickel) film and an Au film are formed in order as lamination layers on the electrode pad pattern of the Al film or further formed a Ti (titanium) film between the Al film and the Ni film.
FIG. 4 shows a prior art of a structure of a circuit device containing a high frequency thin film coil. In the figure, a wiring pattern 2 of an Al (aluminum) film and an electrode pad pattern 4 are formed on a bottom side surface of a Si-IC substrate 1 (the bottom is upward shown in the figure) in a wafer process. Though an insulation protection of a passivation film 3 is formed on the wiring pattern 2, some part of the electrode pad pattern 4 of the Al film corresponding to a putting part of a metallic bump 12 should be exposed for instance by photo lithography. The bump 12 is provided through which an electrical connection is achieved with another substrate by the flip chip bonding, or other bonding methods.
If the metallic bump 12 is directly connected to the electrode pad pattern 4, a diffusion phenomenon is caused and voids are generated on the joint side of the Al film, because the metallic bump 12 is formed with Au or the like. Consequently, the generated voids might cause the decrease in joint strength. To evade the diffusion phenomenon, the UBM consisting of lamination layers are formed one by one on the electrode pad pattern 4 of the Al film. The lamination layers include for instance a Ni film 6 and an Au film 7 as the uppermost layer.
On the other hand, the wiring pattern 2 to compose a coil 5 (inductive element) was put under an insulation protection by the passivation film 3, and was irrelevant to the UBM processing.
Though the above-mentioned circuit device which contains a high frequency thin film coil is used for instance as a device for the wireless telecommunications equipment, in order to minimize a loss in a transmission side and to improve filtering effect in a reception side, the improvement of Q characteristic of the coil becomes a main subject.
In general, a thickness of an Al deposited film formed in a wafer process is usually suppressed to a minimum thickness of necessary, that is about 0.5 μm from a viewpoint of balancing electric performance with manufacturing cost. Therefore, there was a limit so as to form the coil of high Q and low direct current resistance in an adjacent formation on an IC substrate in case of considering the coil formed with the Al film of the said thickness. For instance, if the value of inductance is 3 nH, the value of Q lowers to become about 5–6, such value of Q will not satisfy requirements for a composition element of a filter or the like.
When a high density device formation is requested to the IC substrate, the coil shapes inevitably becoming small and the accumulation space of the magnetic energy of the coil is small, and it becomes difficult more and more to obtain a high Q characteristic, as the wiring pattern of the Al film forming the coil conductor becomes thin. The value of Q is inverse proportion to an energy loss, as a result, though the Q characteristic is improved when the loss is a little, it is difficult to keep the high Q characteristic by the above-mentioned reason in order to realize the miniaturizing electronic parts.
Japanese Patent Application Laid-Open No. 2002-57292, No. 9-330817, and No. 8-172161 are examples of showing a device containing a coil (inductive element) in a semiconductor substrate.
In Japanese Patent Application Laid-Open No. 2002-57292, a plurality of chip formation areas are arranged on a semiconductor wafer substrate, and a circuit element formation area is arranged in each chip formation area, and a coil (inductive element) is formed with a conductor layer on the circuit element formation area from which the conductor layer is insulated by a insulation layer so as to miniaturize the coil. However it is necessary to give some production process where the coil is formed independently. Therefore there is a defect that production steps will increase.
In Japanese Patent Application Laid-Open No. 9-330817, an electrolytic plating conductor layer is formed after a spiral coil conductor of an electroless plating conductor layer is formed on a silicon substrate, so as to increase the total thickness of the coil conductor and to improve Q value. However, a formation of a contacting part and the formation of the coil are practiced separately.
In Japanese Patent Application Laid-Open No. 8-172161, a structure is disclosed which has a resin insulation film formed on a half insulation semiconductor substrate, and a wiring metal layer for an inductance element on the resin insulation film. A low ratio permittivity material is used for the resin insulation film and a thickness of which is increased, consequently a capacity between the lines of the wiring metal is decreased so as to improve Q value. There is no description that refers a coil formed on a semiconductor substrate having bumps for electrical connection.